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HS-6664RH
September 1995
Radiation Hardened 8K x 8 CMOS PROM
Pinouts
5
Features
* 1.2 Micron Radiation Hardened Bulk CMOS * Total Dose 3 x 10 RAD (Si) * Transient Output Upset >5 x 108 RAD (Si)/s * LET >100 MEV-cm2/mg * Fast Access Time - 35ns (Typical) * Single 5V Power Supply * Single Pulse 10V Field Programmable * Synchronous Operation * On-Chip Address Latches * Three-State Outputs * NiCr Fuses * Low Standby Current <500A (Pre-Rad) * Low Operating Current <15mA/MHz * Military Temperature Range -55
oC
28 LEAD CERAMIC SBDIP CASE OUTLINE D28.6 MIL-STD-1835, CDIP2-T28 TOP VIEW
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 28 VDD 27 P 26 NC 25 A8 24 A9 23 A11 22 G 21 A10 20 E 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3
to
+125oC
Description
The Intersil HS-6664RH is a radiation hardened 64K CMOS PROM, organized in an 8K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and utilizes synchronous circuit design techniques to achieve high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with microprocessors that use a multiplexed address/data bus structure. The output enable control (G) simplifies system interfacing by allowing output data bus control in addition to the chip enable control (E). All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location. Applications for the HS-6664RH CMOS PROM include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, and processor control storage.
28 LEAD FLATPACK CASE OUTLINE K28.A MIL-STD-1835, CDFP3-F28 TOP VIEW
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
P must be hardwired at all times to VDD, except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
840
518741 3197.3
HS-6664RH Functional Diagram
MSB A2 A3 A4 A5 A6 A7 A8 LSB
A LATCHED ADDRESS REGISTER 8 A 8 E E 32 32 32 32 32 32 32 32 256 GATED ROW DECODER 256 X 256 MATRIX
1 OF 8
P
8 E E A G E 5 A 5 GATED COLUMN DECODER PROGRAMMING, AND DATA OUTPUT CONTROL 8 Q0 - Q7
LATCHED ADDRESS REGISTER
MSB A0 A1 A10 A9 A11 A12
LSB
P must be hardwired at all times to VDD, except during programming. TRUTH TABLE E 0 0 1 G 0 1 X MODE Enabled Output Disabled Disabled
Spec Number 841
518741
Specifications HS-6664RH
Absolute Maximum Ratings
Supply Voltage (All Voltages Reference to Device GND). . . . . +7.0V Input or Output Voltage Applied for All Grades. . . . . . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC Braze Seal DIP Package . . . . . . . . . . . . . 40.0oC/W 4.0oC/W Braze Seal Flatpack Package . . . . . . . . . 53.4oC/W 6.0oC/W Maximum Package Power Dissipation at +125oC Braze Seal DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.75W Braze Seal Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 936mW Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26,817 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. (NOTES 1, 2) CONDITIONS VDD = 4.5V, IO = -2.0mA VDD = 4.5V, IO = 100A VDD = 4.5V, IO = 4.8mA VDD = 5.5V, G = 5.5V, VI/O = GND or VDD VDD = 5.5V, VI = GND or VDD, P Not Tested VDD = 5.5V, IO = 0mA, VI = VDD or GND VDD = 5.5V, G = VDD, (Note 3), f = 1MHz, IO = 0mA, VI = VDD or GND VDD = 4.5V (Note 4) GROUP A SUBGROUPS 1, 2, 3 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 3.5 VDD -0.3V -10.0 -1.0 MAX 0.4 10.0 1.0 500 15 UNITS V V V A A A mA
PARAMETER High Level Output Voltage Output High Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Standby Supply Current Operating Supply Current Functional Test NOTES:
SYMBOL VOH1 VOH2 VOL IOZ II IDDSB IDDOP
FT
7, 8A, 8B
-55oC TA +125oC
-
-
-
1. All voltages referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. Typical derating = 15mA/MHz increase in IDDOP. 4. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.45V, IOH = -1mA, IOL = +1mA, VOH 1.5V, VOL 1.5V.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. LIMITS PARAMETER Output Enable Access Time Chip Enable Access Time Address Setup Time Address Hold Time SYMBOL TGLQV TELQV TAVEL TELAX (NOTES 1, 2, 3) CONDITIONS VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 5 12 MAX 20 60 UNITS ns ns ns ns
Spec Number 842
518741
Specifications HS-6664RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Guaranteed and 100% Tested. LIMITS PARAMETER Chip Enable Low Width Chip Enable High Width Read Cycle Time NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume transition time 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1 TTL equivalent load and CL 50pF. 3. All tests performed with P hardwired to VDD. 4. Address Access Time (TAVQV) = TELQV + TAVEL = 65ns (maximum). SYMBOL TELEH TEHEL TELEL (NOTES 1, 2, 3) CONDITIONS VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 60 20 80 MAX UNITS ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS, AC AND DC (NOTE 2) CONDITIONS VDD = Open, f = 1MHz VDD = Open, f = 1MHz VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V LIMITS NOTES 1, 3 1, 3 3 3 3 3 TEMPERATURE TA = +25oC TA = +25oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 5 5 MAX 15 12 15 15 UNITS pF pF ns ns ns ns
PARAMETER Input Capacitance I/O Capacitance Chip Enable Time Output Enable Time Chip Disable Time Output Disable Time NOTES:
SYMBOL CIN CI/O TELQX TGLQX TEHQZ TGHQZ
1. All measurements referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after design or process changes which would affect these characteristics.
TABLE 4. POST 100K RAD AC AND DC ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: All AC and DC parameters are tested at the +25oC pre-irradiation limits.
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Standby Supply Current Input Leakage Current SYMBOL IDDSB IOZ II Output Low Voltage Output High Voltage VOL VOH DELTA LIMITS 50A 1A 100nA 60mV 400mV
Spec Number 843
518741
Specifications HS-6664RH
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA 1 and 2 Final Test Group A Group B (*Optional) Group C (Optional) Group D (Optional) Group E, Subgroup 2 (Note 1) NOTE: 1. Intersil may exercise its option to perform to a small lot sampling plan of 5 units per lot. B5 Others METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 Samples/5005 Samples/5005 Samples/5005 Samples/5005 -Q SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B 1, 7,9 N/A 1, 7, 9 1, 7, 9 -8 SUBGROUPS 1, 7, 9 1, 7, 9 1, 7 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 N/A N/A 1, 7, 9 1, 7, 9 1, 7, 9
Timing Waveform
READ CYCLE
TAVQV 3.0V 1.5V 1.5V VALID ADDRESS ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V E TEHEL G 1.5V TGLQX TELQX VALID DATA TS TELQV TGLQV 1.5V 0V TGHQZ TEHQZ 3.0V 1.5V 1.5V 1.5V 0V VALID ADDRESSES 0V
DATA OUTPUT Q0 - Q7
Spec Number 844
518741
HS-6664RH Burn-In Circuits
HS1-6664RH 28 LEAD (8K x 8 PROM DIP) HS9-6664RH 28 LEAD (8K x 8 PROM FLATPACK)
VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC DQ0 DQ1 DQ2 VSS VDD P NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 NC NC NC NC NC NC F13 F8 F7 F6 F5 F4 F3 F2 F1 LOAD LOAD LOAD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD P NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 LOAD LOAD LOAD LOAD LOAD NC F9 F10 F12 F0 F11 F0
HS1-6664RH 28 LEAD (8K x 8 PROM DIP) HS9-6664RH 28 LEAD (8K x 8 PROM FLATPACK)
VDD
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15 LOAD: 10K OUT
VSS = GND
VSS = GND
VDD/2
STATIC CONFIGURATION NOTES: 1. Power Supply: VDD = 5.5V (Min) 2. Resistors = 10k 10%
DYNAMIC CONFIGURATION NOTES: 1. Power Supply: VDD = 5.5V (Min) 2. VIH = VDD to VDD-1.0V 3. VIL = 0.0V to 0.8V 4. Resistors = 10K 10% 5. F0 = 100KHz 10%, 50% Duty Cycle 6. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2; F5 = F4/2; . . . F13 = F12/2
Irradiation Circuit
HS1-6664RH 28 LEAD (8K x 8 PROM DIP)
VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD P NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 NC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD = GND
NOTES: 1. Power Supply: VDD = 5.5V 2. All Resistors = 47K 10%
0.5V
Spec Number 845
518741
HS-6664RH Intersil - Space Level (-Q) Product Flow (Note 1)
SEM - Traceable to Diffusion Method 2018 Wafer Lot Acceptance Method 5007 Internal Visual Inspection Method 2010, Condition A Gamma Radiation Assurance Tests Method 1019 Nondestructive Bond Pull Method 2023 Customer Pre-Cap Visual Inspection (Note 2) Temperature Cycling Method 1010, Condition C Constant Acceleration Method 2001, Condition E Min, Y1 Particle Impact Noise Detection Method 2020, Condition A Electrical Tests (Intersil' Option) Serialization X-Ray Inspection Method 2012 Electrical Tests - Subgroup 1; Read and Record (T0) Static Burn-In Method 1015, Condition B, 72 Hrs, +125oC Min. Interim 1 Electrical Tests - Subgroup 1; Read and Record (T1) Burn-In Delta Calculation (T0 -T1) PDA Calculation 3% Subgroup 7 5% Subgroups 1, 7, Dynamic Burn-In Method 1015, Condition D, 240 Hrs, +125oC (Note 3) Interim 2 Electrical Tests - Subgroup 1; Read and Record (T2)
NOTES: 1. The notes of Method 5004, Table 1 shall apply; Unless Otherwise Specified. 2. These steps are optional, and should be listed on the individual purchase order(s), when required. 3. Intersil reserves the right of performing burn-in time temperature regression as defined by Table 1 of Method 1015. 4. Data package contains: Assembly Attributes (post seal) Test Attributes (includes Group A) Shippable Serial Number List Radiation Testing Certificate of Conformance Wafer Lot Acceptance Report (Including SEM Report) X-Ray Report and Film Test Variables Data
Alternate Group A - Subgroups 1, 7, 9; Method 5005; Para 3.5.1.1 Burn-In Delta Calculation (T0 - T2) PDA Calculation 3% Subgroup 7 5% Subgroups 1, 7, Electrical Tests - Subgroup 3; Read and Record Alternate Group A - Subgroups 3, 8B, 11; Method 5005; Para 3.5.1.1 Marking Electrical Tests - Subgroup 2; Read and Record Alternate Group A - Subgroups 2, 8A, 10; Method 5005; Para 3.5.1.1 Gross Leak Tests Method 1014, 100% Fine Leak Tests Method 1014, 100% Customer Source Inspection (Note 2) Group B Inspection Method 5005 (Note 2) End-Point Electrical Parameters: B-5 - Subgroups 1, 2, 3, 7, 8A, 8B, 9, 10, 11; B-6 - Subgroups 1, 7, 9 Group D Inspection Method 5005 (Notes 2, 4) End-Point Electrical Parameters: Subgroups 1, 7, 9 External Visual Inspection Method 2009 Data Package Generation (Note 4)
Intersil -8 Product Flow
Internal Visual Inspection Method 2010 Condition B Alternate Gamma Radiation Assurance Tests Method 1019 Customer Pre-Cap Visual Inspection (Note 1) Temperature Cycling Method 1010, Condition C Fine and Gross Leak Tests Method 1014 Constant Acceleration Method 2001 Y1 30KG Initial Electrical Tests Dynamic Burn-In Method 1015, Condition D, 160 Hrs, +125oC +25oC Electrical Tests - Subgroups 1, 7, 9
NOTES: 1. These steps are optional, and must be negotiated as part of order. 2. Group B, C and D data package contains Attributes Data. 3. Intersil reserves the right to perform Alternate Group A. The 5% PDA is still applicable. 4. `-8' Data package contains: Assembly Attributes (post seal) Test Attributes (includes Group A) Radiation Testing Certificate of Conformance Certificate of Conformance (as found on shipper)
PDA Calculation 5% Subgroups 1, 7 Electrical Tests +125oC, -55oC Group A Inspection Method 5005. 5% PDA (Note 3) Brand Customer Source Inspection (Note 1) Group B Inspection Method 5005 (Notes 1, 2) Group C Inspection Method 5005 (Notes 1, 2) Group D Inspection Method 5005 (Notes 1, 2) External Visual Inspection Method 2009 Data Package Generation (Note 4)
Spec Number 846
518741
HS-6664RH Metallization Topology
DIE DIMENSIONS: 271 x 307 x 19 1mils METALLIZATION: M1: 6kA 1kA Si/Al/Cu 2kA 500A TiW M2: 10kA 2kASi/Al/Cu GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 SUBSTRATE POTENTIAL: VDD TRANSISTOR COUNT: 110, 874 GATE COUNT: 27, 719 (Based on 2-Input NAND)
Metallization Mask Layout
HS-6664RH (28) VDD (23) A11 (26) NC (2) A12 (25) A8 (24) A9 (22) G A10 (21) (7) A3 (6) A4 (5) A5 (4) A6 (3) A7 (27) P
VSS
DQ0 (11)
DQ1 (12)
DQ2 (13)
DQ3 (15)
DQ4 (16)
DQ5 (17)
DQ6 (18)
GND (14)
DQ7 (19)
A2 (8)
A1 (9)
A0 (10)
E (20)
VDD
VSS VDD
Spec Number 847
518741
HS-6664RH Packaging
c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH
D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)
28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 5/18/94
E M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS
c c1 D eA E e eA eA/2
e
eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
L Q S1 S2
aaa bbb ccc M N
Spec Number 848
518741
HS-6664RH Packaging (Continued)
A
e
PIN NO. 1 ID AREA
A
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B) 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.460 0.180 0.030 MAX 0.115 0.022 0.019 0.009 0.006 0.740 0.520 0.550 MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 11.68 4.57 0.76 1.27 BSC 0.20 6.35 0.66 0.00 28 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 18.80 13.21 13.97 NOTES 3 3 7 2 8 6 Rev. 0 5/18/94
-A-
-B-
D
A b
S1 b E1
b1 c c1 D
0.004 M Q A -C-
H A-B S
DS E
0.036 M
H A-B S C
DS
E E1 E2
-D-H-
L E3
E2 E3 LEAD FINISH
L
E3 e k L
0.050 BSC 0.008 0.250 0.026 0.00 28 0.015 0.370 0.045 0.0015
SEATING AND BASE PLANE
c1
BASE METAL b1 M M (b) SECTION A-A
(c)
Q S1 M N
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
Spec Number 849
518741
Semiconductor
HS-6664RH
8K x 8 CMOS PROM
DESIGN INFORMATION
September 1995
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Background Information HS-6664RH Programming
PROGRAMMING SPECIFICATIONS PARAMETER Input "0" Voltage "1" Programming VDD Operating VDD Special Verify Delay Time Rise Time Fall Time Chip Enable Pulse Width Address Valid to Chip Enable Low Time Chip Enable Low to Output Valid Time Programming Pulse Width Input Leakage at VDD = VDDPROG Data Output Current at VDD = VDDPROG Output Pull-Up Resistor Ambient Temperature NOTES: 1. All inputs must track VDD (pin 28) within these limits. 2. VDDPROG must be capable of supplying 500mA. VDDPROG Power Supply tolerance 3% (Max.) 3. See Steps 22 through 29 of the Programming Algorithm. 4. See Step 11 of the Programming Algorithm. 5. All outputs should be pulled up to VDD through a resistor of value Rn. 6. Except during programming (See Programming Cycle Waveforms). SYMBOL VIL VIH VDDPROG VDD1 VDD2 td tr tf TEHEL TAVEL TELQV tpw tIP IOP Rn TA MIN 0.0 VDD-2 9.0 4.5 4.0 1.0 1.0 1.0 20 0 90 -10 5 TYP 0.2 VDD 9.0 5.5 1.0 10.0 10.0 100 +1.0 -5.0 10 25 MAX 0.8 VDD+0.3 9.0 5.5 6.0 10.0 10.0 60 110 10 -10 15 UNITS V V V V V s s s ns ns ns s A mA k
oC
NOTES
6 2
3
4
5
Spec Number 850
518741
HS-6664RH
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Background Information Programming
The HS-6664 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the specifications shown, or use of an approved commercial programmer is recommended. Programming Sequence of Events 1. Apply a voltage of VDD1 to VDD of the PROM. 2. Read all fuse locations to verify that the PROM is blank (output low). 3. Place the PROM in the initial state for programming: E = VIH, P = VIH, G = VIL. 4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit. 5. After a delay of td, apply voltage of VIL to E (pin 20) to access the addressed word. 6. The address may be held through the cycle, but must be held valid at least for a time equal to td after the falling edge of E. None of the inputs should be allowed to float to an invalid logic level. 7. After a delay of td, disable the outputs by applying a voltage of VIH to G (pin 22). 8. After a delay of td, apply voltage of VIL to P (pin 27). 9. After delay of td, raise VDD (pin 28) to VDDPROG with a rise time of tr. All outputs at VIH should track VDD within VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resistors of value Rn. 10. After a delay of td, pull the output which corresponds to the bit to be programmed to VIL. Only one bit should be programmed at a time. 11. After a delay of tpw, allow the output to be pulled to VIH through pull-up resistor Rn. 12. After a delay of td, reduce VDD (pin 28) to VDD1 with a fall time of tf. All outputs at VIH should track VDD with VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resistors of value Rn. 13. Apply a voltage of VIH to P (pin 27). 14. After a delay of td, apply a voltage of VIL to G (pin 22). 15. After a delay of td, examine the outputs for correct data. If any location verifies incorrectly, it should be considered a programming reject. 16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM. Post-Programming Verification 17. Place the PROM in the post-programming verification mode: E = VIH, G = VIL, P = VIH, VDD (pin 28) = VDD1. 18. Apply the correct binary address of the word to be verified to the PROM. 19. After a delay of td, apply a voltage of VIL to E (pin 20). 20. After a delay of td, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 21. Repeat steps 17 through 20 for all possible programming locations. Post-Programming Read 22. Apply a voltage of VDD2 = 4.0V to VDD (pin 28). 23. After a delay of td, apply a voltage of VIH to E (pin 20). 24. Apply the correct binary address of the word to be read. 25. After a delay of TAVEL, apply a voltage of VIL to E (pin 20). 26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 27. Repeat steps 23 through 26 for all address locations. 28. Apply a voltage of VDD2 = 6.0V to VDD (pin 28). 29. Repeat steps 23 through 26 for all address locations.
Spec Number 851
518741
HS-6664RH
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
HS-6664RH PROGRAMMING CYCLE
PROGRAMMING VDDPROG A VIH VIL td E VIH VIL td VDDPROG VIH G VIL td P VIH VIL td VDDPROG VDD VDD GND tr VDDPROG VIH/VOH Q VIL/VOL td tpw td tf td VALID VALID TEHEL VERIFY
READ DATA
HS-6664RH POST PROGRAMMING VERIFY CYCLE
VIH VIL TAVEL VIH VIL TEHEL 6.0V 5.0V 4.0V VDD td td VALID TEHEL TEHEL
A
E
0.0V TELQV VOH VOL READ TELQV TELQV
Q
READ
READ
Spec Number 852
518741
HS-6664RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 853

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